Data processing system having emulation capability for providing wait state simulation function

ABSTRACT

An emulator for use in a data processing system for providing simulation of the machine wait state of the emulated central processor. A combination of hardware, firmware and software is provided to allow processing in the native mode of the data processing system while the emulated processor is in the wait state. Means are also provided for rapidly returning from the wait state to the emulation process in response to an emulator specific pending allowable interrupt. Means are further provided for indicating to the operator whether the emulated processor can in fact exit from the wait state and further means are provided for indicating to the operator the length of time the emulated processor has been in the wait state.

United States Patent [191 Coulter et al.

[ DATA PROCESSING SYSTEM HAVING EMULATION CAPABILITY FOR PROVIDING WAIT STATE SIMULATION FUNCTION {75] Inventors: Brent W. Coulter, Bellingham,

Mass; Laurence F. Migdalek, Bethesda, Md.

[73] Assignee: Honeywell Information Systems Inc..

Waltham, Mass.

22 Filed: Dec. 17,1973

21 Appl. No.1 425,661

[ June 24, 1975 3.440.612 4/1969 Womack 340/l72.5

Primary E.ramz'ner.loseph M. Thesz, Jr. Attorney, Agent, or Firm-John S. Solakian; Ronald T.

Reiling [57] ABSTRACT An emulator for use in a data processing system for providing simulation of the machine wait state of the emulated central processor. A combination of hardware, firmware and software is provided to allow pro cessing in the native mode of the data processing system while the emulated processor is in the wait state. Means are also provided for rapidly returning from the wait state to the emulation process in response to an 521 U.S. Cl. 340/1725 [5|] Int. Cl. G06F 9/18 emulator speclfic Pendmg allowable mten'upt- Means 58 Field of Search 340/1725 are further Provided for indicating the Operator whether the emulated processor can in fact exit from [56] Refemnces Cited the wait state and further means are provided for indi- UNITED STATES PATENTS eating to the operator the length of time the emulated processor has been in the wait state. 3297.999 l/l967 Shimabukuro 340/l72.5 3.374.466 3/1968 Hanf et al 340/1725 17 Claims, 62 Drawing Figures F m sses l 05.) EMULATORS ance cowunrrow oom T DEX-GE |u-- M Um \50 m no PERIPHERAL j J umr PORTS I01 I00 0- suFFER STORE 1' 7 mum/em 5 -9 552%; 05:10:

ncu u 5&2550 wasysrfu ONE PERIHIEIAL suasrsrru venom venom m... m m m I 1 2 s 4 I SHEET PATENTEDJUH24 ms PATENTEDJUN 24 I975 .13. 8531, 9 T4 SHEET 2 FIG. 2 an no. 0 3! GENERAL REGISTER 7 202- TAGIRIIIG STN sTE OFFSET arr no. I 3 4 F a I 17 TAG RING STN sTE OFFSET err no. 0 I 2 '3 4 T a 9 i5 E BASE REGISTER, INSTRUCTION GOUNTER, AND STAGK REGISTER mTIssA s cIIARIIcTERIsTIc BIT no. 0 IS I6 25 24 MANTISSA 2057 an no s9 47 5s a QGIENTIFIG REGISTER (oouaLEwofl BIT no. 0 2T BOUNDARY ADDRESS REGISTER cc LRN on an un M52 207 err no. 0 2 a 4 5 e T STATUS REGISTER ME Rs ASR AME ET GE HG RIEJZOB BIT Ma 0 I 2 a 4 5 s HARDWARE CONTROL MASK REGISTER LEGEND FOR RESERVED AREAS OF STORAGE IN REGISTERS AME ACCOUNTING MECHANISM HG HARDWARE GATE s SIGN AsR AuTo sToRAsE LRN LAST RING NUMBER sTE SEGMENT TABLE REooIIEIGuRATIoII ENTRY IIIIaz MUST BE ZERO em BINARY MASK STN sEsuIEIIT TABLE ME MACHINE ERRoR NUMBER so CONDITION cooE Rm RING RuuaER TAG DESGRIPTOR CE coRREcTEo ERRoR TYPE RI-Iu REsERvEo FOR on nEcIuIIIL MASK RARowARE usE um UNgERFLOW ET 5 ENVIRONMENT TOLERANCE R5 RETRY SUCCESSFUL PATENTEI] JUN 24 I975 SHEET 3 MEMORY LOCATION 0 CURRENT STATE ENTRY TmE -s2 READY TmE Amoumme -24 wmms TmE momma -|s aurmms TIME AOOOUNT -a RESIDUAL TIME OUT m miss 0 CAPABILITY PRIORITY STATE 05x1 4 STATUS uaz MP ulaz I2 OETSZ DETA l6 srwsz STVIA 2o STWSZ 5" 20 T oomEm's 32 1c CONTENTS BASE REGISTERS savms AREA (a mans) GENERAL REGISTERS SAVING AREA 05 nouns) WORDS) FIG. 4

NAME:

GET

RTA

OPTIONAL WTIONAL PATENTEDJUN24|91s 3 891' 974 SHEET 4 BAR /5OI 5 SYSTEM BASE J-TABLE POINTER 503 J TABL J P NUMBER NUMBER PBG 7A STACK SEGMENT 700 unuszo T REGISTER Poanou TOP OF STACK WORK AREA 101 save mm couuumcmous AREA FIG. 6

RESERVED FOR HARDWARE ABSOLUTE ADDRESS 0 BAR -a- J TABLE WORD BAR 4 G TABLE WORD BAR 8 --h- A SYSTEM EXCEPTION CELL #O SYSTEM EXCEPTION CELL #1 SYSTEM EXCEPTION CELL #2 60 SYSTEM EXCEPTION CELL #3 SYSTEM EXCEPTION CELL #4 SYSTEM EXCEPTION CELL#5 SYSTEM EXCEPTION CELL-#6 SYSTEM EXCEPTION CELL #7 SYSTEM EXCEPTION CELL #8 BAR 44 CHANNEL EXCEPTION CELL BAR 48 I- INTERNAL PROCESSOR QUEUE WORD BAR 52 sYsTBNI BASE INITIAL CURRENT NFS RETRY RETRY COUNT couNT BAR 56 RUNNING PROCESS WORD BAR 60 ABSOLUTIZATION TABLE POINTER BAR+64 CPU SERIAL NUMBER BAR 68 c- MAIN STORAGE UPPER LIMIT BAR-+72 BAR+84 RESTART CELL BAR M 502 SYSTEM BASE J-TABLE POINTER G-TABLE POQNTER INTERNAL PROCESS FIG. 8

SEGMENT GO QUEUE WORD (\POW) READY QUEUE wmmc OUEUES nuuums 6 TABLE PROCESS WORD G o eo1\ s3 64 RUNNING PROCESS PCB ssemzu'r- 6n PATENTEI] JUII 2 4 I975 SHEET 8 I00 I002 I003 I004 F CAPABILITY PRIORITY STATE DEXT BYTE BYTE BYTE NUMBER ACCOUNTING MODE I005 SCIENTIFIC MODE I005 000E MODE CAPABILITY IOOT o o o 0 FIG IOb \IOOI I008 I009? mm FIG IOc l0l3 I0I2 I0I4 I0II IOI5 IOlQ- -IOIG A 5 55 01:10:10 olwlOOB err osmon o I 2 a 4 5 STATUS MBZ MP MBZ I FIG IOe IOI6 IOIT IOIB I0Is J 0 1 0 l5 Is 524 5| an no.

maz SE0 '7 SRA FIG lOf 0 s 1 7 a l5/\B 2 524 sI aIT n0.

MEANINGLESS EXCEPTION CLASS m0 TYPE PATENTEDJUN24 I975 389L974 SHEET 9 nasal cam an no. 0 i F G 3T swim saw F \I an no. 0 '7 a h 5| r MB2/\/2B see (sm, STE) mo RELATIVE ADDRESS ERA/I029 MBZ m FIG. IOQ

PATENTEUJUM24 I915 3.891, 974

SHEET 10 non- 002- an NO 0 JTSZ 7 a J TABLE POINTER 45'] FIG. 110

U037 04- L5 PTSZ P TABLE POUNTER Tl BIT NO. 7 8 l FIG. 11b

uos nos- 01- P maz PRocEss couTRoL Bwcx Pomten J BIT NO. 0 I 7 8 3| FIG. 11c

uoe "097 an No. 0 GTSZ 7 a 6 TABLE POINTER 431 FIG. 11d

m2 ms nu m4 "I071 A u w Gg-ms 7 WORD o i use (x n61 SIZE (X I6) BIT NO. 32 39 PATENTED M 2 4 1915 SHEET 1 1 L 01 HT NO.

HEAD OF O/PR/RDY M25 M26 M27 "F5 mrrm. ouaazm I I arm couu'r arm COUNT arr no. 0 \5 i1 2 24 H31 u2an29 H337 NFS m a E ARM JP arruo. 0 1a mammals 3| FIG 11 j ATSZ ABSOLUUZAT'ON TABLE POINTER CPU SERIAL NUMBER BIT NO. 0

FIG. 11 Q PATENTEDJUN 24 1915 SHEEI MAIN STORAGE UPPER LIMIT BIT NO. 0 I 3 4 BIT NO.

k RSU BIT NO.

FIG. 11m

ISL DEVICE CN-fi IMROWARE DEVICE CN# FIG. 1 in FIG. 11o

SUBTYPE HARDWARE DEVICE TYPE RSU ISL DEVICE TYPE suarvv:

FIG. 11p

IIIBZ FIG. T1

RESERVED FOR IIULTIPROCESSOR EXTENSION FIG.- 11 r PATENTEDJUN 24 I975 SHEET 1 4 [307 CENTRAL PRocEssINs uNIT (CPU) I04 GENERAL REGISTERS I308 I309 aAsE REGISTERS scIENTIFIc REGISTERS T- REGISTER sTATus REGISTER J?" INsTRucTIDN COUNTER (1c) HARDWARE CONT. MASK REG l3l3 l3l5/ SCRATCH PAD o 0 D o a I n a o 0 MEMORY CONTROL UNIT (LSU) UNIT DATA A MANAGE- INsTRucTIoN Cu) TIMING IvIENT FETCH UNIT l3|9 SIGNALS UNIT /EMULATION (IFU) To ALL (DMU) I3|6 UNIT FRACT'ONAL l32l UNITS (EIA) ARITH. LOGIC (ALU) MEM- I o a o a 0 0 o I n -Aux, |3|9u MEM,

MICRO OPERATION BRANCH coNDITIoN SIGNALS To I323 SIGNALS FROM B22 FUNCTIONAL FUNCTIONAL uNITs UNITS I302 I50| I I f W 'X'E CONTROL STORE ADAPTER (cIA) (csu) 13057 (I304 [I303 INPUT/OUTPUT CONTROL AND CONTROL STORE CONTROL UNIT (3 LOAD UNIT LOADER Ioc (CLU) (CSL) M|C R0 INSTRUCTIONS PATENTEDJuu24 I975 3,891,974

SHEET 16 BIT YES

I482 IS PRNaARN YES I483 SET AB AND ARN IN BAR +56 ASYNCHRONOUS T R A P RUN EMULATION M P IS DEXT=O? YES RUN NORMAL M ODE (I326 [I327 [I328 [I329 [I330 (IISSI CON TA T MAIN SEQUENCE BRANCHING E g O DATA FIELD TYPE AND /OR A D TO MICRO-OPS CHECKING USES MICRO-OPS DESIGNATION BUS FIELD E A a c o L QA QB N E K F p -|325 6 4 6 6 I 4 4 BITS 3 F/G. I30

PATENTEDJUN24 I975 3,891,974

SHEET 1 7 D I s 1401 FETCH IPQW FROM SYST. BASE TO SCRATCH PAD FGO-FETCH GO SEQ. DESC CUR RENTLY RUN IN FETCH HEAD OF READY QUEUE- (so, IPQW) RUN HEAD OF READY QUEUE mus FETCH PR'ORITY BYTE OF CURRENT PROCESS [CJP) FROM PROCESS MAIN WORD O PMW O IS CJP OF LOWER PRIORITY THAN PROCESS AT HEAD OF READY l4l4 (misc R ESET CONTEST QUEUE NJP? INDICATOR NEXT INST EMULATION MODE FIRMWARE PRIORITY sua l4l8 |4|9 NEXT INST. NATIVE MODE FIRMWARE RLLO SUBROUTINE FIG. I40

PATENTEDJUN24 I975 3.891, 974

I430 Fl A SUBBWTI NFE j FETCH CBA ACCE$S BAR 423 FETCH PMW 3 FETCH RUNNING PROCESS WORD (RPw) AT I43 BAR+56 I424 FETCH f PMW 0 PLACE PROCESS L|NK(PL) IN RPW (WRITE NJP IN RPW) I425 TEST: I f MBZ FIELD ILLEGAL PCB 0F PMWO DEQUEUE PL FROM Q/PR/RDY 14250 FETCH C FIRMWARE 3 MW SUBROUTINE LJQLK I435 6 f [#42 PLACE OLD TEST; RPW, JP No, IN MBZ FIELD ILLEGAL PCB A PROCESS OF PMW I $0 LINK IN Q/PR/RDY =0 W427 SET /4C PROCESSOR TO VACANT PATENTED M 2 4 I975 SHEET FETCH ASW o w I L 0F Aswo ILLEGAL PCB MUST BE 41 7 FETCH AswI Fl L 0F Asw 1 ILLEGAL PCB MUST BE S8 FETCH EXCEPTION WORD EXW TEST MBZ FIELD ILLEsALPcB 0F EXW :0

FIG. /40' FETCH STOCK WORD SKW TEST

MBZ FIELD ILLEGAL PCB OF SKW $0 FETCH INSTRUCTION COUNTERWORD I C W I445 I f TEST OF ICW #0 FETCH MBZ WORD ERIE D MBZ WORD FETCH STACK BASE wonos 0,I,2 (saw 0,1,2)

FIG /48 

1. A data processing system comprising: A. a central processing unit for executing instructions in a native mode; B. an emulation unit, coupled with said central processing unit, for executing instructions in a non-native mode, in order to emulate the operation of another central processing unit; C. first means for indicating whether said central processing unit emulated by means of said emulation unit is in a wait state wherein no further emulation unit processing may continue; D. second means for indicating whether there is a pending interrupt; E. third means for indicating whether said pending interrupt is allowable; F. means for enabling further processing in said native mode of said central processing unit while said emulated processing unit is in the wait state, and G. means responsive to said second and third means for indicating for again continuing execution in said non-native mode if said interrupt is pending and allowable.
 2. A system as in claim 1 further comprising: A. fourth means for indicating the period of time of said wait state condition; said B. means, responsive to said fourth means for indicating, for informing the operator of said central processing unit of said wait state condition at predetermined intervals.
 2. a wait state counter,
 2. said first means for indicating, said first means for indicating including a wait state bit for indicating said wait state when said wait state bit is in a first binary state; and B. means responsive to the first binary state in said wait state bit and the indication of a pending allowable interrupt for executing another program.
 3. means for changing the value of said timer at a predetermined rate,
 3. A system as in claim 1 wherein said second means for indicating comprises: A. an interrupt flag word including a plurality of locations; and B. means for processing said interrupts in order to indicate at least one pending interrupt in one location of said interrupt flag word.
 4. A system as in claim 3 wherein said means for processing comprises: A. means for receiving a plurality of first interrupts indicating input or output events; B. means for receiving a second interrupt; C. semaphore means for storing messages including the origin of said first and second interrupts; D. means for decoding said messages; and E. fifth means for indicating an interrupt of said first and second types in said interrupt flag word if said first and/or second interrupts include messages which indicate that said interrupts are associated with and/or result from the processing in said emulation unit.
 4. means for generating a first signal each time said timer value changes by a first value,
 5. means, responsive to said first signal, for changing the value of said counter by a second value,
 5. A system as in claim 4 further comprising: A. means for generating said second interrupt in response to an operator''s request or in response to the timeout of a predetermined interval of time; and wherein B. said locations in said interrupt flag word are each capable of storing bits of information, each bit in a first binary state indicating a pending interrupt, wherein a plurality of said bits of information are indicative of said plurality of first interrupts, and wherein at least one of said bits of information are indicative of said second interrupt.
 6. A system as in claim 4 wherein said third means for indicating comprises: A. a system mask including a plurality of locations corresponding to the number of locations in said interrupt flag word; B. means for comparing like numbered locations in Said system mask and said interrupt flag word; and C. means for generating a pending interrupt allowable signal if said like numbered locations include similar binary states and if said fifth means for indicating indicates an interrupt of said first and/or second type.
 6. means for comparing the value of said counter with a third value, and
 7. means, responsive to said means for comparing, for providing a wait state prompting signal to said operator each time said value of said counter is equal to or greater than said third value.
 7. A system as in claim 6 further comprising: A. a hard wait state flag for indicating that said emulated central processing unit is not presently emulatable; and B. means for setting said hard wait state flag if each of the locations in said system mask indicate a second binary state.
 8. A system as in claim 6 wherein a first binary state in said like numbered locations of said interrupt flag word and said system mask indicate a pending allowable interrupt and wherein a second binary state in either one of said like numbered locations indicates that there is no pending allowable interrupt.
 9. A system as in claim 6 further comprising: A. a counter for indicating whether there are any messages in said semaphore means; B. means for incrementing said counter each time a message is removed from said semaphore means, whereby a zero count indicated by said counter indicates that there are no messages in said semaphore means.
 10. A system as in claim 6 further comprising: A. a program status word associated with a first program and including
 11. A data processing system comprising: A. a central processing unit for executing instructions in a native mode; B. an emulation unit, coupled with said central processing unit, for executing instructions in a non-native mode, in order to emulate the operation of another central processing unit; C. first means for indicating whether said central processing unit emulated by means of said emulation unit is in a wait state wherein no further emulation unit processing may continue, and D. means for informing the operator of said central processing unit of said wait state condition at predetermined intervals, said means for informing comprising
 12. A system as in claim 11 wherein said first value is equal to said second value.
 13. A system as in claim 11 wherein said means for informing further comprises: A. an accumulator for maintaining the total time of said wait state; B. means, responsive to said counter, for changing the value of said accumulator in proportion to the change in value of said counter each time said counter value is changed by said second value; C. means for resetting the value in said counter each time said prompting signal is provided.
 14. A system as in claim 13 wherein said means for informing further comprises means for resetting the values in both said counter and said accumulator each time said emulation unit exits from said wait state.
 15. A data processing system comprising: A. a central processing unit for executing instructions in a native mode; B. an emulation unit, coupled with said ceNtral processing unit, for executing instructions of a process in a non-native mode, in order to emulate the operation of another central processing unit; C. first means for indicating whether said emulation unit emulating said another central processing unit indicates that said emulation unit, i.e., said another unit as emulated, is in a wait state wherein no further emulation unit processing may continue; D. means for enabling further processing in said native mode of said central processing unit while said emulation unit is in the wait state; E. second means for indicating whether there is a pending interrupt; F. third means for indicating whether processing of said pending interrupt is allowable; and G. means responsive to said second and third means for indicating for again continuing execution in said non-native mode if said interrupt is pending and allowable.
 16. A system as in claim 15 further comprising means for informing the operator of said central processing unit of said wait state condition at predetermined intervals.
 17. A data processing system comprising: A. a central processing unit for executing instructions in a native mode; B. an emulation unit, coupled with said central processing unit, for executing instructions of a process in a non-native mode, in order to emulate the operation of another central processing unit; C. first means for indicating whether said emulation unit emulating said another central processing unit indicates that said emulation unit, i.e., said another unit as emulated, is in a wait state wherein no further emulation unit processing may continue; D. means for enabling further processing in said native mode of said central processing unit while said emulation unit is in the wait state; E. a hard wait state flag for indicating that said emulated central processing unit is not presently emulatable; F. means for indicating if interrupts are allowable; and G. means for setting said hard wait state flag if no interrupts are allowable. 